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Features
* Stereo Audio DAC
2.7V to 3.3V Analog Supply Operation 2.4V to 3.3V Digital Supply Operation 20-bit Stereo Audio DAC 90 dB SNR Playback Stereo Channels 32 Ohm/20 mW Stereo Headset Drivers with Master Volume and Mute Controls Stereo Line Level Input with Volume Control/Mute and Playback through the Headset Drivers - Accepts Mixed Signals from All Signal Paths (Line Inputs and DAC Output) - 8, 11.024, 16, 22.05, 24, 32, 44.1 and 48 kHz Sampling Rates - 256x or 384xFs Master Clock Frequency - I2S Serial Audio Interface * Mono Audio Power Amplifier - Supply Input from Main Li-Ion Battery (3V to 5.5V) - 440 mW on 8 Ohm Load - Programmable Volume Control (-22 to +20 dB) - Fully Differential Structure, Input and Output - 8 mA Drain Current in Active Mode - Power-down Mode (Consumption Less than 2 A) - Minimum External Components (Direct Connection to the Loudspeaker) * Applications: Mobile Phones, Digital Cameras, PDAs, SmartPhones, DECT Phones, Music Players - - - - - -
Power Management and Analog Companions (PMAAC) AT73C240 Audio Interface for Portable Handsets
1. Description
The AT73C240 is a fully integrated, low-cost, combined stereo audio DAC and audio power amplifier circuit targeted for Li-Ion or Ni-Mh battery powered devices such as mobile phones, smartphones, PDA, DECT phones, digital still cameras, music players or any other type of handheld device where an audio interface is needed. The stereo DAC section is a complete high performance, stereo, audio digital-to-analog converter delivering a 90 dB dynamic range. It comprises a multibit sigma-delta modulator with dither, continuous time analog filters and analog output drive circuitry. This architecture provides a high insensitivity to clock jitter. The digital interpolation filter increases the sample rate by a factor of 8 using 3 linear phase half-band filters cascaded, followed by a first order SINC interpolator with a factor of 8. This filter eliminates the images of baseband audio, retaining only the image at 64x the input sample rate, which is eliminated by the analog post filter. Optionally, a dither signal can be added that reduces possible noise tones at the output. However, the use of a multibit sigma-delta modulator already provides extremely low noise tone energy. Master clock is 256 or 384 times the input data rate, allowing choice of input data rate up to 48 kHz, including standard audio rates of 48, 44.1, 32, 16 and 8 kHz. The DAC section is followed by a volume and mute control and can be simultaneously played back directly through a stereo 32 Ohm headset pair of drivers. The stereo 32 Ohm headset pair of drivers also includes a mixer of a LINEL and LINER pair of stereo inputs.
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High quality mono output is provided. The DAC output can be connected through a buffer stage to the input of the audio power amplifier, using 2x coupling capacitors The mono buffer stage also includes a mixer of the LINEL and LINER inputs which can be, for example, the output of a voice Codec output driver in mobile phones. The Audio Power Amplifier is a differential amplifier designed in CMOS technology. It is capable of driving an 8 Ohm Loudspeaker at maximum power of 440mW, making it suitable as a hands-free speaker driver in a Wireless Handset Application. The volume, mute, power down, de-emphasis controls and 16-bit, 18-bit and 20-bit audio formats are digitally programmable via a 4-wire SPI bus or via a 2-wire TWI bus and the digital audio data are provided through a multi-format I2S interface.
2. Block Diagram
Figure 2-1. AT73C240 Functional Block Diagram
PAINN
PAINP
HPP
CBP
VBAT
HPN
GNDB
VREF
AT73C240
VDIG AVDD AVDDHS SPI_DOUT
Audio PA
Voltage Reference
-36 to +12dB / 3dB step
LINER PGA
SPI_DIN / TWD INGND
-36 to +12dB / 3dB step
LINEL PGA
Status Registers
SPI
SPI_CLK / TWCK SPI_CSB / TW_ADD
-6 to +6dB / 3dB step
HSL 32 driver +
-46.5dB to 0dB / 1.5dB step -34.5dB to +12dB / 1.5dB step
Volume Control + Volume Control
MCLK RSTB Serial Audio I/F
DAC
Digital Filter
SMODE SDIN LRFS BCLK
VCM
-6 to +6dB / 3dB step
HSR GNDA MONOP MONO MONON + 32 driver + DAC Volume Control + Volume Control Digital Filter
-46.5dB to 0dB / 1.5dB step -34.5dB to +12dB / 1.5dB step
GNDD
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3. Pin Description
Table 3-1.
Pin Name VREF AVDD HSL HSR AVDDHS LINEL LINER INGND VCM NC HPN VBAT HPP CBP PAINN PAINP SDIN BCLK LRFS MCLK RSTB SMODE GNDD VDIG SPI_DOUT SPI_DIN/TWD SPI_CLK/TWCK SPI_CSB/TW_ADD MONON MONOP NC NC GNDA
Pin Description
I/O I I O O I I I I I N/A O I O O I I I I I I I I GND I O I/O I I O O N/A N/A GND Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 (Bottom) Type Analog Supply Analog Analog Supply Analog Analog Analog Analog N/A Analog Supply Analog Analog Analog Analog Digital Digital Digital Digital Digital Digital Ground Supply Digital Digital Digital Digital Analog Analog N/A N/A Ground Function Voltage reference pin for decoupling Analog supply (DAC + Line in + Mono out) Left channel headset driver output Right channel headset driver output Headset driver analog supply Left channel line in Right channel line in Line signal ground pin for decoupling Common mode reference for decoupling Not Connected Negative speaker output Audio amplifier supply Positive speaker output Audio amplifier common mode voltage decoupling Audio amplifier negative input Audio amplifier positive input Audio interface serial data input Audio interface bit clock Audio interface left/right channel synchronization frame pulse Audio interface master clock input Master reset (active low) Serial interface selection (to connect to ground) Digital ground Digital supply SPI data output SPI data input / TWI data input SPI clock / TWI clock SPI chip select / TWI address bit Negative monaural driver output Positive monaural driver output Not Connected Not Connected Analog ground
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4. Electrical Characteristics
Table 4-1. Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Operating Temperature (Industrial)..............-40 C to +85 C Storage Temperature-...................................55C to +150C Power Supply Input on VBAT-...........................................................0.3V to +5.5V on VDIG, AVDD, AVDDHS-...............................0.3V to +3.6V
5. Digital IOs
All the digital IOs: SDIN, BCLK, LRFS, MCLK, RSTB, SMODE, SPI_DOUT, SPI_DIN/TWD, SPI_CLK/TWCK, SPI_CSB/TW_ADD are referred to as VDIG. Table 5-1.
Symbol VIL VIH VOL VOH
Digital IOs
Parameter Low level input voltage High level input voltage Low level output voltage High level output voltage Conditions Guaranteed input low Voltage Guaranteed input high Voltage IOL = 2 mA IOH = 2 mA VDIG from 2.4Vto 3.3 V from 2.4Vto 3.3 V from 2.4Vto 3.3 V from 2.4Vto 3.3 V VDIG - 0.5V Min -0.3 0.8 x VDIG Max 0.2 x VDIG VDIG + 0.3 0.4 Unit V V V V
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6. Audio Power Amplifier
6.1 Electrical Specifications
VBAT = 3.6V, TA = 25C unless otherwise noted. 100 nF capacitor connected between CBP and GNDA, 470nF input capacitors, load = 8 Ohms. Table 6-1.
Symbol VDD IDD IDDstby VCbp VOS ZIN ZLFP CL PSRR FCL
Audio Power Amplifier Electrical Specifications (General Conditions: VDD = 3.6V,TA = 25C)
Parameter Supply voltage Quiescent current Standby current DC reference Output differential offset Input impedance Active state, minimum gain Output load Capacitive load Power supply rejection ratio Low Frequency Cutoff Between each output and the ground 200 to 2 kHz differential output 1 kHz reference frequency 3 dB attenuation Maximum gain 1 KHz reference frequency 3 dB attenuation Maximum gain Off to on mode Voltage already settled Input capacitors precharged Max gain, A weighted 1 kHz Pout = 3mW to 300mW gain = 2dB 1 KHz load 8 ohms -2 -0.7 440 0 0 2 0.7 120 20 60 25 40 100K 6 150k 8 200k 32 100 Ohms pF dB Hz Full gain, capacitive input coupling Active state, maximum gain -20 10K VDD/2 0 15k 20 20k Ohms Inputs shorted, no load Conditions Min 3 Typ 3.6 6 Max 5.5 12 2 Unit V mA A V mV
FCH
High Frequency Cutoff
kHz
tUP VN THD
Output setup time Output noise Output distortion
10 500 50
ms VRMS dB
Pmax GACC GSTEP
Maximum power Overall Gain accuracy Gain Step Accuracy
mW dB dB
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7. Audio DAC
7.1 Electrical Specifications
AVDD, AVDDHS = 2.7 V, TA = 25C, typical case, unless otherwise noted. All noise and distortion specifications are measured in the 20 Hz to 0.425xFs range and A-weighted filtered. Full-scale levels scale proportionally with the AVDD / AVDDHS supply voltage. Table 7-1.
Overall Operating Temperature (ambient) Analog Supply Voltage (AVDD, AVDDHS) Digital Supply Voltage (VDIG) DIGITAL INPUTS/OUTPUTS Resolution Logic Family Logic Coding Analog Performance - DAC to Line-out/Headphone Output Output level for full scale input (for AVDD, AVDDHS = 2.8 V) Output common mode voltage Output load resistance (on HSL, HSR) Headphone load Line load Output load capacitance (on HSL, HSR) Headphone load Line load Signal to Noise Ratio (-1dBFS @ 1kHz input and 0dB Gain) Line and Headphone loads, A-Weighted Total Harmonic Distortion (-1dBFS @ 1kHz input and 0dB Gain) Line Load Headphone Load Headphone Load (16 Ohm) Dynamic Range (measured with -60 dBFS @ 1kHz input, extrapolated to full-scale), A Weighted Line Load Headphone Load Interchannel mismatch Left-channel to right-channel crosstalk (300 Hz to 20kHz) Output Headset Driver Level Control Range Output Headset Driver Level Control Step Maximum output power, headphone 32 Ohms load, 1% THD -5 2.5 15 6.20 1.75 0.5 x AVDDHS 16 32 10 30 30 90 1000 150 mVrms Vpp V 20 CMOS 2's Complement bits -40 2.7 2.4 +25 2.8 2.8 +85 3.3 3.3 C V V
Electrical Specifications
Min Typ Max Units
Ohms kOhms pF pF dB
-80 -65 -40
-75
dB dB dB
90 80 0.1 -65 5 1
dB dB dB dB dB dB mVrms
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Table 7-1. Electrical Specifications (Continued)
Min Maximum output slope at power up (100 to 220 F coupling capacitor) Analog Performance - Line-in/Microphone Input to Line-out/Headphone Output Output level @ AVDD, AVDDHS = 2.7 V and 0 dB gain, 500mV Rms input level, 2 X 10k Ohms loads (HSL, HSR) @ AVDD, AVDDHS = 2.7 V and 20 dB gain, 500mV Rms input level, 2 X 32 Ohms loads (HSL, HSR) Input common mode voltage Input impedance Signal to Noise Ratio 500mV Rms @ 1kHz input and 0 dB gain 50mV Rms @ 1kHz input and 20 dB gain Dynamic Range (extrapolated to nominal 500mV level) -60 dBr (500 mVrms)@ 1kHz input and 0 dB gain (10k Ohms load) -60 dBr 50 mVrms) @ 1kHz input and 20 dB gain (10k Ohms load) Total Harmonic Distortion, A-Weighted, line 10k Ohms load 500mV Rms @ 1kHz input and 0 dB gain 50mV Rms @ 1kHz input and 20 dB gain Total Harmonic Distortion, A-Weighted, line 32 Ohms load 500mV Rms @ 1kHz input and 0 dB gain 50mV Rms @ 1kHz input and 20 dB gain Interchannel mismatch Left-channel to right-channel crosstalk (300Hz to 20kHz) Analog Performance - PA Driver Differential output level for one input 500mV Rms singlel @ AVDD, AVDDHS = 2.8 V Differential output level for stereo inputs 500mV Rms singlel @ AVDD, AVDDHS = 2.8 V, inputs internally summed Output common mode voltage Output load (on each input, DC decoupled to the ground) Gain (one single input to differential output), 20Hz to 20kHz Signal to Noise Ratio (500mV Rms output @ 1kHz) Total Harmonic Distortion (500mV Rms @ 1kHz output) 2 x 10kOhm balanced load 10 -05 500 1 0.5xAVDDHS 50 30 0 80 -80 0.5 mVrms Vrms V kOhm pF dB dB dB 7 80 1.62 570 1.58 560 0.5 x AVDD 10 85 70 85 85 -85 -78 -70 -65 0.1 -65 -80 -70 -60 -55 1 Vpp mVrms Vpp mVrms V kOhm dB dB dB dB dB dB dB dB dB dB Typ Max 3 Units V/s
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Table 7-1.
Master Clock
Electrical Specifications (Continued)
Min Typ Max Units
Master Clock Maximum Long Term Jitter Digital Filter Performance Frequency response (10 Hz to 20 kHz) Deviation from linear phase (10 Hz to 20 kHz) Passband 0.1 dB corner Stopband Stopband Attenuation De-emphasis Filter Performance (for 44.1kHz Fs) MAX deviation from ideal response POWER PERFORMANCE Current consumption from Analog supply in power on Current consumption from Analog supply in power down Power on Settling Time From full power down to full power up (Vref and VCM decoupling capacitors charge) Line in amplifier (line in coupling capacitors charge) Driver amplifier (out driver DC blocking capacitors charge) 500 50 500 9 -1 0.5465 65 0.1 0.1 0.4535
1.5
nspp dB deg Fs Fs dB
1
dB
mA 10 A ms ms ms
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7.2 Digital Filters Transfer Function
Figure 7-1. Channel Filter
Figure 7-2.
Channel Filter
Figure 7-3.
De-emphasis Filter
FR of DAC Decimator with Deemphasis Fs=44100; OSR=128 0
-2
-4 Gain (dB)
-6
-8
-10
-12 10
3
10 Frequency (Hz)
4
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7.3
Data Interface
Normal operation is entered by applying correct LRFS, BCLK and SDIN waveforms to the serial interface, as illustrated in Figure 7-4, Figure 7-5 and Figure 7-6. To avoid noise at the output, the reset state is maintained until proper synchronization is achieved in the serial interface. The data interface allows three different data transfer modes. See Figure 7-4, Figure 7-5 and Figure 7-6.
Figure 7-4.
BCLK
20-bit I2S Justified Mode
LRFS
SDIN
R1
R0
L(N-1)
L(N-2)
L(N-3)
...
L2
L1
L0
R(N-1)
R(N-2)
R(N-3)
...
R2
R1
R0
Figure 7-5.
BCLK
20-bit MSB Justified Mode
LRFS
SDIN
R0
L(N-1)
L(N-2)
L(N-3)
...
L2
L1
L0
R(N-1)
R(N-2)
R(N-3)
...
R2
R1
R0
L(N-1)
Figure 7-6.
BCLK
20-bit LSB Justified Mode
LRFS
SDIN
R0
L(N-1)
L(N-2)
...
L1
L0
R(N-1)
R(N-2)
...
R1
R0
L(N-1)
The selection between modes is done using the DINTSEL<1:0> signal.
DINTSEL <1:0> 00 01 1x Format I2S Justified MSB Justified LSB Justified
The data interface always works in slave mode. This means that the LRFS and the BCLK signals are provided by the host controller. In order to achieve proper operation, the LRFS and the BCLK signals must be synchronous with the MCLK master clock signal and their frequency relationship must reflect the selected data mode. For example, if the data mode selected is the 20bit MSB Justified, then the BCLK frequency must be 40 times higher than the LRFS frequency.
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7.4 Timing Specifications
The timing constraints of the data interface are described in Figure 7-7 and Table 7-2 below. Figure 7-7. Data Interface Timing Diagram
1 20 M/2+1 M
BCLK
ts1 th1
LRFS
ts2 th2
SDIN
Table 7-2.
Data Interface Timing Parameters
Parameter Min 10 10 10 10 Typ Max Unit ns ns ns ns
ts1 th1 ts2 th2
LRFS set-up time before BCLK rising edge LRFS hold time after BCLK rising edge DIN set-up time before BCLK rising edge DIN hold time after BCLK rising edge
7.5
SMODE Selection
SMODE input is internally pulled up in the AT73C240. This ensures a TWI communication protocole default mode When setting SMODE to 0, SPI communication protocol can also be used. Two cases have to be considered: SMODE=1, TWI protocole SMODE=0, SPI protocole
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8. SPI Interface
8.1 Architecture
The SPI is a three-wire bi-directional asynchronous serial link. It works only in slave mode. The protocol is the following: Figure 8-1. SPI Architecture
SPI_CSB
SPI_CLK
rw a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0
SPI_DIN
d7 d6 d5 d4 d3 d2 d1 d0
SPI_DOUT
8.2
SPI Protocol
On SPI_DIN, the first bit is a read/write bit. 0 indicates a write operation, while 1 is for a read operation. The seven following bits are used for the register address and the eight last ones are the write data. For both address and data, the most significant bit is the first one. In case of a read operation, SPI_DOUT provides the contents of the read register, MSB first. The transfer is enabled by the CSB signal active low. When no operation is being carried out, SPI_DOUT is set high impedance to allow sharing of MCU serial interface with other devices. The interface is reset at every rising edge of SPI_CSB in order to come back to an idle state, even if the transfer does not succeed. The SPI is synchronized with the serial clock SPI_CLK. Falling edge latches SPI_DIN input and rising edge shifts SPI_DOUT output bits. Note that MCLK must run during any SPI write access from address 0x00 to 0x11.
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8.3 SPI Interface Timing
Figure 8-2.
SPI_CSB
Tssen Twl Tc Thsen
SPI Timing
SPI_CLK
Twh Tssdi Thsdi
SPI_DIN
Tdsdo
Thsdo
SPI_DOUT
Table 8-1.
Parameter Tc Twl Twh Tssen Thsen Tssdi Thsdi Tdsdo Thsdo
SPI Timing Parameters
Description SPI_CLK min period SPI_CLK min pulse width low SPI_CLK min pulse width high Setup time SPI_CSB falling to SPI_CLK rising Hold time SPI_CLK falling to SPI_CSB rising Setup time SPI_DIN valid to SPI_CLK falling Hold time SPI_CLK falling to SPI_DIN not valid Delay time SPI_CLK rising to SPI_DOUT valid Hold time SPI_CLK rising to SPI_DOUT not valid Min 150 ns 50 ns 50 ns 50 ns 50 ns 20 ns 20 ns 0 ns Max 20 ns -
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9. TWI Interface
9.1 TWI Architecture
The two-wire interface interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds up to 400 Kbits per second, based on a byte oriented transfer format. The TWI is slave only and has single byte access. The TWI adds flexibility to the power supply solution, enabling LDO regulator and Audio functionnalities and paths to be controlled depending on the instantaneous application requirements. The AT73C240 has the following 7-bit address: 1001000. Attempting to read data from register addresses not listed in this section results in 0xFF being read out. * TWCK is an input pin for the clock * TWD is an open-drain pin driving or receiving the serial data The data put on TWD line must be 8 bits long. Data is transferred MSB first. Each byte must be followed by an acknowledgement. Each transfer begins with a START condition and terminates with a STOP condition. * A high-to-low transition on TWD while TWCK is high defines a START condition. * A low-to-high transition on TWD while TWCK is high defines a STOP condition.. Figure 9-1. TWI Start and Stop conditions
TWD
TWCK Start Stop
Figure 9-2.
TWI transfert format
TWD
TWCK
Start
Address
R/W
Ack
Data
Ack
Data
Ack
Stop
After the host initiates a START condition, it sends the 7-bit slave address defined above to notify the slave device. A read/write bit follows (read = 1, write = 0). The device acknowledges each received byte. The first byte sent after the device address and the R/W bit, is the address of the device register the host wants to read or write. For a write operation the data follows the internal address. For a read operation a repeated START condition needs to be generated followed by a read on the device.
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Figure 9-3.
TWD
TWI Write operation
S ADDR W A IADDR A DATA A P
Figure 9-4.
ADDR
TWI Read operation
W A IADDR A S ADDR R A DATA
* S = Start * P = Stop * W = Write * R = Read * A = Acknowledge * N = Not Acknowledge * DADR= Device Address * IADR = Internal Address
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10. User Interface
Table 10-1.
Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0C 0x10 0x11
Register Mapping
Register DAC_CTRL DAC_LLIG DAC_RLIG DAC_LMPG DAC_RMPG DAC_LLOG DAC_RLOG DAC_OLC DAC_MC DAC_CSFC DAC_MISC DAC_PRECH DAC_RST PA_CRTL Note: Name DAC Control DAC Left Line In Gain DAC Right Line In Gain DAC Left Master Playback Gain DAC Right Master Playback Gain DAC Left Line Out Gain DAC Right Line Out Gain DAC Output Level Control DAC Mixer Control DAC Clock and Sampling Frequency Control DAC Miscellaneous DAC Precharge Control DAC Reset Power Amplifier Control MSB = Bit 7, LSB = Bit 0 Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset State 0x00 0x05 0x05 0x08 0x08 0x00 0x00 0x22 0x09 0x00 0x00 0x00 0x00 0x0F
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10.1 DAC Control Register
Register Name: DAC_CTRL Register Address: 0x00 Reset State: 0x00 Access: Read/Write
7 Not Used
6 ONPADRV
5 ONDACR
4 ONDACL
3 ONLNOR
2 ONLNOL
1 ONLNIR
0 ONLNIL
* ONLNIL Left channel line in amplifier (L to power down, H to power up) * ONLNIR Right channel line in amplifier (L to power down, H to power up) * ONLNOL Left channel line out driver (L to power down, H to power up) * ONLNOR Right channel line out driver (L to power down, H to power up) * ONDACL Left channel DAC (L to power down, H to power up) * ONDACR Right channel DAC (L to power down, H to power up) * ONPADRV Differential mono PA driver (L to power down, H to power up)
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10.2
DAC Left Line In Gain Register
Register Name: DAC_LLIG Register Address: 0x01 Reset State: 0x05 Access: Read/Write
7 Not Used
6 Not Used
5 Not Used
4
3
2 LLIG
1
0
* LLIG: Left channel line in analog gain selector
LLIG<4:0> 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 Gain 20 12 9 6 3 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 < -60 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
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10.3 DAC Right Line In Gain Register
Register Name: DAC_RLIG Register Address: 0x02 Reset State: 0x05 Access: Read/Write
7 Not Used
6 Not Used
5 Not Used
4
3
2 RLIG
1
0
* RLIG: Right channel line in analog gain selector
RLIG<4:0> 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 Gain 20 12 9 6 3 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 < -60 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
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10.4
DAC Left Master Playback Gain Register
Register Name: DAC_LMPG Register Address: 0x03 Reset State: 0x08 Access: Read/Write
7 Not Used
6 Not Used
5
4
3 LMPG
2
1
0
* LMPG: Left channel master playback digital gain selector
LMPG<5:0> 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 Gain 12.0 10.5 9.0 7.5 6.0 4.5 3.0 1.5 0.0 -1.5 -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -12.0 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB LMPG<5:0> 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 Gain -13.5 -15.0 -16.5 -18.0 -19.5 -21.0 -22.5 -24.0 -25.5 -27.0 -28.5 -30.0 -31.5 -33.0 -34.5 mute Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
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10.5 DAC Right Master Playback Gain Register
Register Name: DAC_RMPG Register Address: 0x04 Reset State: 0x08 Access: Read/Write
7 Not Used
6 Not Used
5
4
3 RMPG
2
1
0
* RMPG: Right channel master playback digital gain selector
RMPG<5:0> 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 Gain 12.0 10.5 9.0 7.5 6.0 4.5 3.0 1.5 0.0 -1.5 -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -12.0 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB RMPG<5:0> 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 Gain -13.5 -15.0 -16.5 -18.0 -19.5 -21.0 -22.5 -24.0 -25.5 -27.0 -28.5 -30.0 -31.5 -33.0 -34.5 mute Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
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10.6
DAC Left Line Out Gain Register
Register Name: DAC_LLOG Register Address: 0x05 Reset State: 0x00 Access: Read/Write
7 Not Used
6 Not Used
5
4
3 LLOG
2
1
0
* LLOG: Left channel line out digital gain selector
LLOG<5:0> 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 Gain 0 -1.5 -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -12.0 -13.5 -15.0 -16.5 -18.0 -19.5 -21.0 -22.5 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB LLOG<5:0> 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 Gain -24.0 -25.5 -27.0 -28.5 -30.0 -31.5 -33.0 -34.5 -36.0 -37.5 -39.0 -40.5 -42.0 -43.5 -45.0 -46.5 mute Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
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10.7 DAC Right Line Out Gain Register
Register Name: DAC_RLOG Register Address: 0x06 Reset State: 0x00 Access: Read/Write
7 Not Used
6 Not Used
5
4
3 RLOG
2
1
0
* RLOG: Right channel line out digital gain selector
RLOG<5:0> 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 Gain 0 -1.5 -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -12.0 -13.5 -15.0 -16.5 -18.0 -19.5 -21.0 -22.5 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB RLOG<5:0> 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 Gain -24.0 -25.5 -27.0 -28.5 -30.0 -31.5 -33.0 -34.5 -36.0 -37.5 -39.0 -40.5 -42.0 -43.5 -45.0 -46.5 mute Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
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10.8
DAC Output Level Control Register
Register Name: DAC_OLC Register Address: 0x07 Reset State: 0x22 Access: Read/Write
7 RSHORT
6
5 ROLC
4
3 LSHORT
2
1 LOLC
0
* LOLC: Left channel output level control selector
LOLC 100 011 010 001 000 Gain 5 2.5 0 -2.5 -5 Unit dB dB dB dB dB
* LSHORT: Left channel short circuit indicator Persistent; after being set, bit is not cleared automatically even after the short circuit is eliminated; must be cleared by reset cycle or direct register write operation. * ROLC: Right channel output level control selector
ROLC 100 011 010 001 000 Gain 5 2.5 0 -2.5 -5 Unit dB dB dB dB dB
* RSHORT: Right channel short circuit indicator Persistent; after being set, bit is not cleared automatically even after the short circuit is eliminated; must be cleared by reset cycle or direct register write operation.
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10.9 DAC Mixer Control Register
Register Name: DAC_MC Register Address: 0x08 Reset State: 0x09 Access: Read/Write
7 0
6 0
5 INVR
4 INVL
3 RMSMIN2
2 RMSMIN1
1 LMSMIN2
0 LMSMIN1
* LMSMIN1: Left Channel Mono/Stereo Mixer Left Mixed input enable (H to enable, L to disable) * LMSMIN2: Left Channel Mono/Stereo Mixer Right Mixed input enable (H to enable, L to disable) * RMSMIN1: Right Channel Mono/Stereo Mixer Left Mixed input enable (H to enable, L to disable) * RMSMIN2: Right Channel Mono/Stereo Mixer Right Mixed input enable (H to enable, L to disable) * INVL: Left channel mixer output invert (H to enable, L to disable) * INVR: Right channel mixer output invert (H to enable, L to disable) 10.9.1 Digital Mixer Control The Audio DAC features a digital mixer that allows the mixing and selection of multiple input sources. The mixing/multiplexing functions are described in Figure 10-1. Figure 10-1. Digital Mixer Functions
Left channel
Volume Control
+
2
1
Volume Control
From digital filters
To DACs 1
Volume Control
+
2
Volume Control
Right channel
Note:
When the two mixer inputs are selected, a -6 dB gain is applied to the output signal. When only one input is selected, no gain is applied.
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10.10 DAC Clock and Sampling Frequency Control Register
Register Name: DAC_CSFC Register Address: 0x09 Reset State: 0x00 Access: Read/Write
7 Not Used
6 Not Used
5 Not Used
4 OVRSEL
3 Not Used
2 Not Used
1 Not Used
0 Not Used
* OVRSEL: Master clock selector L to 256 x Fs, H to 384 x Fs Master clock and sampling frequency selection Table 10-2 describes the modes available for master clock and sampling frequency selection. Table 10-2.
OVRSEL 0 1
Master Clock Modes
Master Clock 256 x Fs 384 x Fs
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10.11 DAC Miscellaneous Register
Register Name: DAC_MISC Register Address: 0x0A Reset State: 0x00 Access: Read/Write
7 Not Used
6 VCMCAPSEL
5 DINTSEL
4
3 DITHEN
2 DEEMPEN
1 NBITS
0
* NBITS<1:0>: Data interface word length The selection of input sample size is done using the NBITS field.
NBITS <1:0> 00 01 10 Format 16 bits 18 bits 20 bits
* DEEMPEN: De-emphasis enable (L to disable, H to enable) To enable the de-emphasis filtering the DEEMPHEN signal must be set to high. * DITHEN: Dither enable (L to disable, H to enable) The dither option (added in the playback channel) is enabled by setting the DITHEN signal to high. * DINTSEL<1:0>: I2S data format selector The selection between modes is done using the DINTSEL<1:0> signal.
DINTSEL<1:0> 00 01 1x Format I2S Justified MSB Justified LSB Justified
* VCMCAPSEL: VCM decoupling capacitor selector Low for 10 F, High for 100 F
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10.12 DAC Precharge Control Register
Register Name: DAC_PRECH Register Address: 0x0C Reset State: 0x00 Access: Read/Write
7 Not Used
6 Not Used
5 Not Used
4 PRCHGPDRV
3 PRCHGLNIR
2 PRCHGLNIL
1 PRCHG
0 ONMSTR
* ONMSTR: Master power on control (L to power down, H to power up) * PRCHG: Master pre-charge (H to charge) * PRCHGLNIL: Left channel line in pre-charge (H to charge) * PRCHGLNIR: Right channel line in pre-charge (H to charge) * PRCHGPDRV: Differential mono PA driver pre-charge (H to charge)
10.13 DAC Reset Register
Register Name: DAC_RST Register Address: 0x10 Reset State: 0x00 Access: Read/Write
7 Not Used
6 Not Used
5 Not Used
4 Not Used
3 Not Used
2 Not Used
1 RESFILZ
0 RSTZ
* RSTZ: Active low reset of the audio codec * RESFILZ: Active low reset of the audio codec filter See "Supplies and Start-up" on page 30.
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10.14 PA Control Register
Register Name: PA_CTRL Register Address: 0x11 Reset State: 0x0F Access: Read/Write
7 Not Used
6 Not Used
5 APAON
4 APAPRECH
3
2 APAGAIN
1
0
* APAGAIN<3:0>: Audio power amplifier gain
APAGAIN<3:0> 0000 0001 0010 0011 0100 0101 0110 0111 Gain db FORBIDDEN 20 17 14 11 8 5 2 APAGAIN<3:0> 1000 1001 1010 1011 1100 1101 1110 1111 Gain db -1 -4 -7 -10 -13 -16 -19 -22
* APAPRECH: Audio power amplifier precharge bit * APAON: Audio power amplifier on bit
APAON 0 0 1 1 APAPRECH 0 1 0 1 Operating Mode Stand-by Input capacitors precharge Active mode Forbidden state
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11. Supplies and Start-up
In operating mode, VBAT (supply of the audio power amplifier) must be between 3V and 5.5V and AVDD, AVDDHS and VDIG must be inferior or equal to VBAT and lower than 3.3V. A typical application is VBAT connected to a battery and AVDD, AVDDHS and VDIG supplied by regulators. VBAT must be present at the same time or before AVDD, AVDDHS and VDIG. RSTB must be active (0) until the voltages are stable and reach the proper values. To avoid noise issues, it is recommended to use ceramic decoupling capacitors for each supply close to the package as defined in the application diagram. See Figure 13-1 on page 33. The track of the supplies must be optimized to minimize the resistance, especially on VBAT where all the current from the power amplifier comes from. HPN and HPP must be routed symmetrically and the resistance must be minimized, at the expense of maximum output power capabilities reduction.
11.1
Audio DAC Start-up Sequences
In order to minimize the noise during the start-up, a specific sequence should be applied. In any audio configuration, always force Bit 2 to high level ("1") at 0x0B address.
11.1.1
Power on Example Path DAC to headset output 1. Write @0x10 => 0x03 (deassert the reset) 2. Write @0x0C => 0x1F (precharge + master on) 3. Write @0x00 => 0x0C (ONLNOL and ONLONOR set to 1) 4. Delay 500 ms 5. Write @0x0C => 0x01 (precharge off + master on) 6. Delay 1ms 7. Write @0x00 => 0x3C (ONLNOL, ONLNOR, ONDACR and ONDACL set to 1)
11.1.2
Power off Example 1. Write @0x00 => 0xC0 (ONDACR and ONDACL set to 0) 2. Write @0x0C => 0x00 (master off) 3. Delay 1ms 4. Write @0x00 => 0x00 (all off)
11.1.3
I2S Example In order to prevent I2S from generating noise at the output (for example a MP3 player switching from one song to another): 1. Set ONDAC to 0 ((bit 4 and 5 in register @0x00) 2. Stop I2S and MCLK When I2S is restarted, in order to prevent noise generation at the output: 1. Start MCLK 2. Write @0x10 => 0x00 (RESFILZ=0, RSTZ=0) 3. Write @0x10 => 0x03 (RESFILZ=1, RSTZ=1)
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4. Delay 5 ms 5. Set ONDAC to 1 (bit 4 and 5 in register @0x00) 6. Reprogram all DAC settings (Audio format, gains, etc.) 7. Start I2S.
11.2
Audio Power Amplifier Power on Sequence
To avoid an audible "click" at start-up, the input capacitors must be pre-charged before the power amplifier. 1. At start-up, disable APAON, APAGAIN<3:0> set to -22 dB, enable APAPRECH. 2. Wait 50 ms minimum. 3. Then disable APAPRECH and enable APAON. 4. Wait 10 ms min time. 5. Set the gain to the value chosen.
11.2.1
Audio Power Amplifier Power off Sequence To avoid an audible "click" at power-off, the gain should be set to the minimum gain (-22 dB) before turning off the power amplifier.
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12. Current Consumption in Different Modes
Table 12-1. Curent Consumption in Different Modes
Current Consumption (typ) 5 total 1: Standby Vref generator Vcm generator total 2: DAC Playback Through stereo Headset (Current in the load not included) Vref generator Vcm generator Left line out amplifier Right line out amplifier Left D-to-A converter Right D-to-A converter total Vref generator 3: Stereo DAC Playback to Audio PA (Current in the load not included) Vcm generator Left D-to-A converter Right D-to-A converter Differential mono PA driver Audio PA total 4: Playback From Stereo Line Input to Stereo Headset (Current in the load not included) Vref generator Vcm generator Left line in amplifier Right line in amplifier Differential mono PA driver total 5 0 250 250 0 250 850 850 1600 1600 5150 0 250 1600 1600 800 6000 10650 0 250 700 700 850 2500 Current Consumption (max) 12 12 1 350 351 1 350 1200 1200 2000 2000 6751 1 350 2000 2000 1200 12000 17551 1 350 900 900 1200 3351
Mode 0: Off
Powered up block All blocks off and RSTB = 0
Unit A A A A A A A A A A A A A A A A A A A A A A A A A
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13. Application Diagram
Figure 13-1. Application Using One Li-Ion Battery
PAINN 22u Battery (Li-Ion or 3 x NiMh or NiCd) VBAT 100n C16 CBP C7 8 Ohm Loudspeaker HPN AVDD HPP C18
AT73C240
2.8V from LDO VDIG C17 100n 2.8V from LDO
3.6 V
Audio PA
AVDDHS
100n
C19 10F C15 PAINP C9 470n MONOP 470n MONON R stereo line input (e.g. FM Radio) 470n L 470n C3 LINEL C12 VCM C8 LINER 10u SPI_DOUT SPI_DIN/TWD SPI_CLK/TWCK SPI / TWI
REF
VREF 10u C11
DIG
SPI_CSB/TW_ADD SMODE RSTB Reset active low
C6 32 32 Ohm Headset or Line Out 32 100u 100u C5 HSL 10u INGND C10 GNDA HSR
MCLK
Audio DAC
SDIN LRFS BCLK I2S
GNDD
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14. Components List
Table 14-1.
Reference C3, C8, C12, C15 C5, C6 C9, C10, C11, C19 C7, C17, C18 C16
Components List
Value 470 nF 100 F 10 F 100 nF 22 F Techno Ceramic Ceramic Ceramic Ceramic Ceramic Size 0402 1210 0603 0402 0805 Manufacturer & Reference C1005X5R1A474K (TDK) or GRM155R60J474KE19 (Murata) C3225X5R0J107M (TDK) or GRM32ER60J107ME20 (Murata) C1608X5R0J106MT (TDK) or GRM188R60J106ME47 (Murata) C1005X5R1C104K (TDK) or GRM155R61A104KA01 (Murata) C2012X5R0J226MT (TDK) or GRM21BR60J226ME39 (Murata)
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15. Package Drawing
Figure 15-1.Package OutlineR-QFN032_H
Notes:
1. All dimensions are in mm. 2. Drawing is for general information only. Refer to JEDEC drawing MO-220 for additional information.
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Figure 15-2. Package Drawing with Pin 1 and Marking for R-QFN032_H package
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16. Revision History
Doc. Rev 6464A
Comments First issue
Change Request Ref.
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Headquarters
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
International
Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Product Contact
Web Site www.atmel.com Analog Companions (PMAAC) Technical Support Atmel techincal support pmaac@atmel.com Sales Contacts www.atmel.com/contacts/
Literature Requests www.atmel.com/literature
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